1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a semiconductor device of the insulated gate type and a manufacturing method of the same.
2. Description of the Prior Art
Illustrated in FIG. 6 is a vertical MOS field effect transistor as an example of a conventional semiconductor device of the insulated gate type, which comprises a semiconductor substrate 1 comprised of a drift region in the form of an N-type epitaxially grown layer 1b formed on a drain region in the form of an N.sup.+ -type semiconductor layer 1a, a gate oxide layer 2 partially formed on the main surface of the semiconductor substrate 1, a gate electrode 3 partially formed on the gate oxide layer 2 and an oxide layer 4 formed to cover the gate electrode 3. The vertical Mos field effect transistor is provided with a P-type body region 5 formed by implanting impurities of the P-type into the N-type epitaxially grown layer 1b from the main surface side of the substrate 1 and being spreaded beneath the gate electrode 3, an N.sup.+ -type source region 6 formed by implanting impurities of the P-type in a portion of the P-type body region 5, a P.sup.+ -type body region 7 of approximately the same depth as that of the P-type body region 5 formed by implanting impurities of the P-type in a portion of the N.sup.+ -type source region 6, a source electrode 8 commonly in contact with the N.sup.+ -type source region 6 and P.sup.+ -type body region 7 at the main surface side of the substrate 1 and a drain electrode 9 formed on the back surface of the substrate 1. Illustrated in FIG. 7 is distribution of impurity concentration in a section taken along line VII--VII in FIG. 6. As shown in FIG. 7, the concentration of the N.sup.+ -type source region in the MOS field effect transistor is determined to be higher than that of the P.sup.+ -type body region 7. The reference character NA in FIG. 7 represents an inert impurity concentration.
Illustrated in FIGS. 8(a)-8(i) is a manufacturing process of the conventional vertical MOS field effect transistor. As shown in FIG. 8(a), a drift region in the form of an N-type epitaxial layer 1b is grown on a drain region in the form of an N.sup.+ -type semiconductor layer 1a to provide a semiconductor substrate 1, and a gate oxide layer 2 is formed on the surface of the N-type epitaxial layer 1b. At the following step, a poly-silicon gate electrode 3 containing phosphorus is formed on the gate oxide layer 2 and provided thereon with a first photo-resist layer 3a. As shown in FIG. 8(c), the gate electrode 3 is formed by partly eliminating the photo-resist layer 3a and etching the poly-silicon using the photo-resist layer 3a as a mask. After the photo-resist layer 3a is eliminated, as shown in FIG. 8(d), boron ions B are implanted into the N-type epitaxial layer 1b by using the gate electrode 3 as a mask to form a P-type body region 5 spread beneath the gate electrode 3 by thermal diffusion. Subsequently, as shown in FIG. 8(e), a second photo-resist layer 3b is formed on the gate electrode 3 and P-type body region 5 in such a manner as to expose a portion of the P-type body region 5, and boron ions B are implanted at high concentration by using the photo-resist layer 3b as a mask to form a P.sup.+ -type body region 7 with the depth of the P-type body region 5 by thermal diffusion.
Thereafter, as shown in FIG. 8(f), a third photo-resist layer 3c is formed to cover the P.sup.+ -type body region 7, and arsenic ions As are implanted in the P-type body region 5 and P.sup.+ -type body region 7 by using the photo-resist layer 3c as a mask to form an N.sup.+ -type source region 6 of higher concentration than the P.sup.+ -type body region 7 by thermal diffusion. At the following step, as shown in FIG. 8(g), an oxide layer 4 containing phosphorus P is formed on the gate oxide layer 2 and gate electrode 3, and a fourth photo-resist layer (not shown) is formed on the oxide layer 4. Thus, as shown in FIG. 8(h), the oxide layer 4 is partly etched by using the photo-resist layer as a mask to expose the surface of the P.sup.+ -type source region 6. In such a condition, as shown in FIG. 8(i), a source electrode 8 commonly in contact with the N.sup.+ -type source region 6 and P.sup.+ -type body region 7 is formed on the oxide layer 4 at the main surface side of the substrate 1, and a drain electrode 9 is formed on the back surface of the substrate 1.
In the vertical MOS field effect transistor, as shown in FIG. 6, the on-resistance of the N.sup.+ -type source region 6 is determined by a distance L between each end of the source electrode 8 in contact with the N.sup.+ -type source region 6 and each internal side end of gate electrode 3 and oxide layer 4. However, the distance L may not be defined less than a sum of thickness L.sub.1 of the internal insulating layer and the accuracy L.sub.2 of the mask alignment of the photo resist layer. If the distance L is defined to be less than the sum of the thickness L.sub.1 and accuracy L.sub.2, an actual opening dimension x.sub.1 of the oxide layer 4 is decreased to a dimension x.sub.2 after etching the oxide layer 4 due to a positional deviation of the mask alignment. This causes an increase of the distance L, resulting in an increase of the on-resistance of the N.sup.+ -type source region 6. If the dimension for accuracy L.sub.2 is determined to decrease the on-resistance of the N.sup.+ -type source region 6, it is required to increase the concentration of the N.sup.+ type source region 6.
In the case that the concentration of the N.sup.+ -type source region 6 is increased, the depth of the N.sup.+ -type source region increases, and the base width of a parasitic bipolar transistor related to the P-type body region 5 becomes narrow. As a result, punch-through voltage at the base portion is decreased to cause the occurrence of punch-through puncture. For the reasons described above, it is impossible to enhance the pressure resistance of the P-type body region 5 with reduction of the on-resistance of the N.sup.+ -type source region 6.